The present invention pertains to a semiconductor circuit which can realize high speed and reduce power consumption; especially, power consumption during standby.
To reduce power consumption, efforts have been made to reduce power supply voltage in semiconductor circuits, such as semiconductor circuits comprising MOS transistors. When a semiconductor circuit is operated at a low power supply voltage, in order to increase the speed of operation, it is desired to use transistors with low threshold voltages. On the other hand, when transistors with low threshold voltages are used, leakage current is increased. In particular, leakage current during standby increases significantly. As a result, the power consumption of the semiconductor circuit is increased. Consequently, realization of both high speed and low power consumption for portable electronic devices operated with batteries continues to be a problem.
Various technologies have previously been proposed to realize high speed and lower power consumption for semiconductor circuits. FIGS. 8 and 9 show two circuit examples for realizing high speed during operation and low power consumption during standby.
In the semiconductor circuit shown in FIG. 8, in order to realize high speed during operation, PMOS transistor P10 and NMOS transistor N10 with low threshold voltages are used. A logic circuit, such as an inverter, is constituted with PMOS transistor P10 and NMOS transistor N10. In this case, since MOS transistors with low threshold voltages are used, high-speed response characteristics can be realized even if the power supply voltage is at a low level, such as 1.5 V. However, since MOS transistors with low threshold voltages are used, the current that passes through transistors P10 and N10 is increased. In particular, leakage current of transistors P10 and N10 increases, leading to increase in power consumption. In order to solve this problem, the threshold voltages of these transistors are controlled by supplying different bias currents to transistors P10 and N10 during operation and standby.
As shown in FIG. 8, a threshold control voltage supply circuit 10 is used to supply a bias voltage Vbsp to the well of PMOS transistor P10 and supply a bias voltage Vbsn to the well of NMOS transistor N10. During operation, the threshold voltages of both transistors P10 and N10 are kept at low levels by using bias voltages Vbsp and Vbsn to realize high speed. On the other hand, during standby, the threshold voltages of both transistors P10 and N10 are kept at high levels by using bias voltages Vbsp and Vbsn to reduce leakage current in order to reduce power consumption.
In the circuit example shown in FIG. 9, an NMOS transistor N22 used for restraining leakage current during standby is connected in series with an inverter comprising PMOS transistor P20 and NMOS transistor N20 with low threshold voltages. Said transistor N22 has a high threshold voltage, and its on/off state is switched corresponding to a standby signal SDB.
During operation, the standby signal SDB is kept at a high level, such as a voltage higher than the threshold voltage of transistor N22, so that transistor N22 is kept in the on state. As a result, the source of transistor N20 is connected to ground potential GND via transistor N22, and the inverter comprising transistors P20 and N20 with low threshold voltages can display high-speed response characteristics. On the other hand, during standby, the standby signal SDB is kept at a level lower than the threshold voltage of transistor N22, such as 0 V. As a result, transistor N22 is in an off state, and the path of leakage current is cut off so that power consumption during standby can be reduced.
In the aforementioned conventional semiconductor circuits, however, in order to form transistors, the well structure is complicated by forming triple wells. Also, it is necessary to significantly change the manufacturing process. The number of manufacturing steps is increased because the number of masks is increased, and the manufacturing cost is also increased. In the semiconductor circuit shown in FIG. 8, since different bias voltages are supplied to the PMOS transistor and NMOS transistor, it is necessary to include a booster in the threshold control voltage supply circuit. As a result, both the layout area of the circuit and the power consumption are increased. In the semiconductor circuit shown in FIG. 9, since it is necessary to form NMOS transistors with different threshold voltages, the number of steps in the process is increased. On the other hand, in order to restrain leakage current during standby, an NMOS transistor used as a switching transistor is connected in series with the current path. This is undesired for realizing high speed. Also, when the number of transistors increases, the layout area is increased significantly.
The objective of this invention is to solve the aforementioned problems by providing a semiconductor circuit which can realize high speed and low power consumption while keeping the increase in manufacturing cost and layout area at a minimum level.
A semiconductor circuit having a logic circuit, which includes a MOS transistor, and a bias voltage supply circuit which selectively supplies a first bias voltage or a second bias voltage which are different from each other to the substrate region of the aforementioned MOS transistor corresponding to a control signal.
In the present invention, preferably, the aforementioned bias voltage supply circuit includes a first MOS transistor connected between a first voltage supply line and a bias voltage supply line and a second MOS transistor connected between a second voltage supply line and the aforementioned bias voltage supply line, and the aforementioned first or second bias voltage is output from the aforementioned bias voltage supply line by turning on the aforementioned first MOS transistor or second MOS transistor.
Also, in the present invention, preferably, the MOS transistor of the aforementioned logic circuit is connected to the aforementioned first voltage supply line.
In addition, in the present invention, preferably, the MOS transistor of the aforementioned logic circuit as well as the aforementioned first MOS transistor and second MOS transistor are PMOS transistors.
Moreover, in the present invention, preferably, the aforementioned logic circuit includes NMOS transistors connected between the aforementioned PMOS transistors and a third voltage supply line, and the aforementioned first voltage is lower than the aforementioned second voltage.